Computers - Intel making a mistake with DDR3?

In the first half of the next year Intel Corp. will be launching its next evolution of its Core microarchitecture, codenamed Nehalem and probably launched as Core 3.

The most radical change there is the move from the FSB bus interface and adoption of a complex, high-speed bus interface developed by Intel which unifies the platforms for Workstation and low end Server Xeon and HPC and cluster Itanium² processors, dubbed CSI (common system interface).
This will be followed by a new on-chip memory controller which will significantly reduce latencies at memory access, increase available bandwidth and improve multisocket scaling in general over current chipsets featuring external memory controller.

Intel will then also use new DDR3 memory, which is projected to run at significantly higher speed standards while consuming less power thanks to reduction in voltage requirement.
But that will be followed by very high latencies, a problem encountered when comparing DDR2 to DDR1 as well.
Having seen the performance hit AMD processors, that have been featuring an on-die memory controller for some time now, took after switching to a DDR2 platform and therefore higher memory latencies, the question arises whether or not Intel will have problems as well after the implementation of their on-chip memory controller since DDR3 memory latencies will be up to two times as high as on current DDR2 memory.
In any case Intel needs to drop FB-DIMM for Xeon because Workstations rarely use the amount of memory Fully Buffered memory is projected to be used for. At least the buyer should be able to choose between regular Registered ECC memory and FB-DIMM.

Intel should really work on latency reduction now. "Just in case..."